This invention relates generally to voltage controlled oscillators. More particularly, it relates to improved bias voltage generators and differential delay stages for high frequency voltage controlled oscillators.
Voltage controlled oscillators are commonly used in phase locked loops (PLLs) which are utilized in various applications where maintaining sequential operations by a clocked pulse is desired. By way of example, computers, tuning receivers, and data communications systems often use PLLs for sequential management of internal operations or for extracting clock information from received signals. PLLs are often implemented in CMOS technology because of their relatively low standby power consumption, relative high manufacturing density, high input impedance, and ability to operate from a wide range of voltages.
Referring initially to FIG. 1, a block diagram of a typical phase lock loop with its various stages and feedback processes will be described. A reference clock signal 2 having a specified frequency and phase is input into a phase detector 4. The phase detector 4 detects the phase difference between the reference clock signal 2 and a feedback signal 12 and sends a corresponding error signal to a charge pump 6. The error signal causes the charge pump to pump or withdraw charge accordingly and to output a signal to loop filter 8. The output of the loop filter, in turn, is used to control a voltage controlled oscillator (VCO) 10 to adjust the phase and frequency of the output signal. The output from the VCO is then fed back (feedback signal 12) to the phase detector 4 where its phase is compared to that of the reference clock signal 2 in a recursive fashion. In a phase lock condition, the phase of the signal output from the oscillator is fixed relative to the reference signal and has a frequency that is a multiple of the reference signal's frequency.
One of the problems inherent with phase locked loops is that it is difficult to maintain a constant frequency under varying conditions such as ambient temperature and variations in power supply voltage. This is because the frequency is a function of the open loop gain of the PLL 1 which is affected by such varying conditions. There are also variations in frequency response of the VCO to a given input voltage from chip-to-chip due to process variations from manufacturing. Process variations are variations in chip characteristics, such as transistor gain, that differ from manufacturing lot to lot or from variations that result from different supplier manufacturing processes of different suppliers.
Referring to FIG. 2, a prior art VCO invertor stage circuit 10 is shown that includes a process variation circuit 12 for adjusting oscillation frequency to compensate for the above-described process variations. The process variation circuit 12 includes a P-channel transistor 14 and an N-channel transistor 16 connected in parallel with their sources tied together and their drains tied together, respectively. The sources of transistors 14 and 16 are coupled to the output of the VCO (which is often referred to as the "invertor" in the art). The gate of transistor 14 is connected to an LP2 input 18 and the drains of transistors 14 and 16 are connected to the gate of an N-channel transistor 20. The source and drain of transistor 20 are grounded such that the transistor serves as a capacitor. The effect of the process variation circuit 12 is to slow down oscillations that are above nominal, as will be discussed in greater detail subsequently. Unfortunately, the process variation circuit 12 is not as effective in speeding up oscillations that are below nominal.
It is particularly difficult to design PLLs for high frequency applications (above 50 Megahertz) since the open loop gain of the PLL can vary significantly due to these varying conditions and process variations. Typically, process variations that result in high gain, i.e. faster transistors than nominal, are referred to in the industry as a "best case process." Similarly, process variations that result in slower transistors are referred to as a "worst case process."
FIG. 3 illustrates typical gain curves for the nominal case process 22 (desired operation), the best case process 23 (faster transistors), and the worst case process (slower transistors) for a typical prior art invertor (VCO). The curves show that the input voltage LP2 at input 18 must vary over a wide range (about 2 V) when operating at a frequency of about 50 MHz due, primarily, to process variations. At 50 MHz, for example, a nominal gain curve 22 typically has an input voltage of around 2 V. An input voltage LP2 at input 18 for the gain curve of a best case process 23 is reduced to around 1 V whereas the input voltage LP2 at input 18 for the worst case process 24 is about 3 V. It is often difficult to design a circuit to provide an input voltage of that can cover that wide a range, and as can be seen in FIG. 3, the range gets wider with higher operating frequencies.
With advancing technology, devices are designed for higher frequencies therefore requiring corresponding increases in gain, as can be seen in any of the operating curves of FIG. 3. Since noise is related to the gain, the increase in gain also dramatically increases the noise in the system thereby increasing the VCOs susceptibility to noise. This noise comes mainly from the power supply VDD and ground VSS where it is introduced from the operation of logic circuits. The high gain causes increased susceptibility to noise that may lead to output signal jitter making it unacceptable for many applications.
The process variation circuit 12 in FIG. 2 compensates to adjust the oscillation frequency of the invertor (VCO). During a scenario where the delay stage frequency is high, a high input level at LP2 18 causes the resistance seen at the sources of the P-channel transistor 14 and N-channel transistor. 16 to be small and the capacitance of transistor 20 seen at the gate to be large thus causing a slowdown in the delay stage. In a scenario where the delay frequency is slow due to a low input level at LP2, the resistance at the sources of transistors 14 and 16 is high causing an isolation of the capacitor 20 and thereby reducing its effect on the delay stage.
One of the disadvantages of circuit 12 is that it mainly only affects the best case process where the capacitor 20 slows down the invertor, whereas the capacitor becomes isolated in the worst case process thus having a negligible affect. Furthermore, previous problems with VDD noise are still present, for example, when VDD drops the gain increases dramatically. For a typical 100 Megahertz per Volt (MHz/V) gain a 1 mV increase in control voltage may result in a 0.1 MHz increase in noise. Also, since the VCO operates only after a sufficient turn on voltage for the transistors is achieved, when the reference clock stops the VCO control voltage drops to zero (falls off) thus stopping oscillation.
Another technique used in the past in to reduce VDD noise was to add a filtering circuit consisting of resistance and capacitance to the power supply to filter out the noise. A disadvantage with this approach is that the resulting voltage drop across the filter reduces the voltage supplied to the phase locked loop. As circuit frequencies increase, the voltage requirements of the phase locked loop may increase to the point where sufficient voltage is not available for operation. The filtering circuit also only filters noise associated with the P-channel transistors of the current source in the oscillator and does not provide increased protection from noise for the N-channel transistors. Accordingly, it is desirable to obtain a high frequency VCO with relatively low gain with improved noise rejection characteristics utilizing a common mode rejection circuit.